The present invention relates to a semiconductor device, and more particularly, to a sensing characteristic evaluating apparatus for a semiconductor device and method thereof, which evaluates a current sensing characteristic for a semiconductor device by sensing a current of a semiconductor memory cell.
A semiconductor device performs a read operation by outputting data stored in a semiconductor memory cell through a local input/output line.
FIG. 1 is a circuit diagram illustrating a conventional memory device for performing a data read operation.
The conventional memory device shown in FIG. 1 includes a current-voltage converting unit 10, a sense amplifier 20, a switching unit 30 and a memory cell 40.
The current-voltage converting unit 10 includes a first PMOS transistor M1, a first NMOS transistor M2 and a second PMOS transistor M3. The first PMOS transistor M1 drives a current of the local input/output line LIO for providing the sensing input voltage SAIN in response to a current control signal ILDB. The first NMOS transistor M2 switches a connection between the local input/output line LIO and the first PMOS transistor M1. The second PMOS transistor M3 is coupled in parallel with the first NMOS transistor M2 through the local input/output line LIO, and switches a pre-charge voltage VPCG to the local input/output line LIO. The current control signal ILDB is applied to a gate of the first PMOS transistor M1, and a clamp control signal CLMP is applied to gates of the first NMOS transistor M2 and the second PMOS transistor M3.
The sense amplifier 20 compares and amplifies a sensing input voltage SAIN of the current-voltage converting unit 10 with a reference voltage VREF, and outputs an amplified sensing input voltage as a sensing output voltage SAOUT.
The switching unit 30 selectively connects a local input/output line LIO of the current-voltage converting unit 10 to the memory cell 40.
The switching unit 30 includes a transfer gate T1 and an inverter IV1, and is turned on/off in response to an input/output line switching signal LIOSW.
The operation of the conventional semiconductor device will be described in details as below.
If a normal mode operation for reading data stored in the memory cell 40 is started, the input/output line switching signal LIOSW is shifted to a logic high level, and the memory cell 40 is coupled to the local input/output line LIO. At the same time, the first NMOS transistor M2 is turned off and the second PMOS transistor M3 is turned on in response to the clamp control signal CLMP having a logic low level. That is, the pre-charge voltage VPCG is applied to the local input/output line LIO in response to the clamp control signal CLMP having a logic low level, and the local input/output line LIO is pre-charged as a node between the first NMOS transistor M2 and the switching unit 30.
If the clamp control signal CLMP is shifted to a logic high level, the second PMOS transistor M3 is turned off and the first NMOS transistor is turned on. When the clamp control signal CLMP has a logic high level, the current control signal ILDB applied to a gate of the first PMOS transistor M1 maintains a logic low level, and a current path is formed from a sensing voltage VSA terminal to the memory cell 40.
A voltage level of the sensing input voltage SAIN inputted to the sense amplifier 20 is determined by a resistance ratio of the first PMOS transistor M1, the first NMOS transistor M2, the local input/output line LIO, the switching unit 30 and the memory cell 40.
A voltage corresponding to the current which flows on the current path from the sensing voltage VSA terminal to the memory cell 40 is applied to the sensing input voltage SAIN as an output voltage of the current-voltage converting unit 10.
If the memory cell 40 is configured to have at least two different resistance values depending on a phase of data, a current quantity which flows on the current path from the sensing voltage VSA terminal to the memory cell 40 depends on the resistance values. In conclusion, a voltage level difference of the sensing input voltage SAIN outputted from the current-voltage converting unit 10 occurs. The sense amplifier 20 compares, detects and amplifies the sensing input voltage SAIN with a reference voltage VREF, and outputs an amplified voltage as the sensing output voltage SAOUT.
A semiconductor device having high integrated circuits includes a plurality of memory cells and a plurality of sense amplifiers. However, since the sense amplifiers have different characteristic based on a location and a fabricating process, evaluating distribution and deviation values according to characteristics of the sense amplifiers is desirable.